Novel Multi-Precision Floating-Point Multiplier Architecture
| dc.Advisor | Tomar Singh, Geetam | en |
| dc.Advisor | Gift, Stephan | en |
| dc.DateSubmitted | 2019 | |
| dc.DegreeType | Doctor of Philosophy (PhD) | en_US |
| dc.Department | Electrical & Computer Engineering | en_US |
| dc.Faculty | Engineering | en_US |
| dc.Institution | University of the West Indies (Saint Augustine, Trinidad and Tobago) | en_US |
| dc.LCCallNumber | TK7895.A65 G46 2019 | en |
| dc.contributor.author | George, Marcus Lloyde | |
| dc.date.accessioned | 2022-10-04T13:35:47Z | |
| dc.date.available | 2022-10-04T13:35:47Z | |
| dc.identifier.uri | https://hdl.handle.net/2139/54418 | |
| dc.relation.uri | https://hdl.handle.net/2139/56284 | |
| dc.rights | Please contact the West Indiana Division at the University of the West Indies,St.Augustine in order to view the full thesis. Contact: wimail@sta.uwi.edu | en_US |
| dc.subject | Computer science -- Mathematics | en |
| dc.subject | Logic, Symbolic and mathematical | en |
| dc.subject | Computer architecture | en |
| dc.subject.lcsh | Arithmetic Circuits | en_US |
| dc.subject.lcsh | Floating-Point Multiplier | en_US |
| dc.subject.lcsh | Multi-Precision Floating Point | en_US |
| dc.subject.lcsh | Arithmetic Logic | en_US |
| dc.subject.lcsh | FPGAs in Arithmetic | en_US |
| dc.title | Novel Multi-Precision Floating-Point Multiplier Architecture | en_US |
| dc.type | Theses | en_US |